1. Field of the Invention
The present invention relates to an SR flip-flop having a differential output function.
2. Description of the Related Art
SR flip-flops that include a set terminal and a reset terminal, in which the output level of the SR flip-flop is switched in response to the signals input to the set terminal and the reset terminal, are widely employed in electronic circuits. FIGS. 1A and 1B each show a circuit diagram showing a configuration of a typical SR flip-flop and a time chart showing the operation thereof. FIG. 1A shows a circuit diagram of a NAND SR flip-flop and an operation waveform diagram thereof. The NAND SR flip-flop includes an inverting set terminal #S and an inverting reset terminal #R. An SR flip-flop 200 switches the output Q to the high-level state in response to a negative edge of an inverted set signal #S, and switches the output Q to the low-level state in response to a negative edge of an inverted reset signal #R. In the present specification and the drawings, the symbols “#” and bar “-” represent logical inversion.
The lower graph in FIG. 1A shows the operation waveform for the SR flip-flop 200. When the inverted set signal #S is asserted (negative edge is detected), the non-inverted output (which will also be referred to simply as the “output”) Q is switched to the high-level state after a propagation delay Tpd due to a NAND gate 202. Furthermore, the inverted output #Q is switched to the low-level state after the propagation delay Tpd due to a NAND gate 204. When the inverted reset signal #R is asserted (negative edge is detected), the inverted output #Q is switched to the high-level state after the propagation delay Tpd due to the NAND gate 204. Furthermore, the output Q is switched to the low-level state after the propagation delay Tpd due to the NAND gate 202.
That is to say, such a NAND SR flip-flop has a problem in that the output Q and the inverted output #Q do not transit simultaneously. With such an arrangement, the switching sequence of the output Q and the inverted output #Q in the reset operation is the opposite of the sequence in the set operation. Accordingly, a simple skew adjustment cannot cancel out the timing gap between the output Q and the inverted output Q#.
FIG. 1B shows an SR flip-flop 300 including NOR gates 302 and 304 and the operation waveform for the SR flip-flop 300. With the SR flip-flop 300 using NOR gates, the switching timing of the output Q does not match the inverted output #Q. Such a problem will also be referred to as “asymmetrical”.